? semiconductor components industries, llc, 2000 august, 2000 rev. 4 1 publication order number: mc14562b/d mc14562b 128-bit static shift register the mc14562b is a 128bit static shift register constructed with mos pchannel and nchannel enhancement mode devices in a single monolithic structure. data is clocked in and out of the shift register on the positive edge of the clock input. data outputs are available every 16 bits, from 16 through bit 128. this complementary mos shift register is primarily used where low power dissipation and/or high noise immunity is desired. ? diode protection on all inputs ? fully static operation ? cascadable to provide longer shift register lengths ? supply voltage range = 3.0 vdc to 18 vdc ? capable of driving two lowpower ttl loads or one lowpower schottky ttl load over the rated temperature range maximum ratings (voltages referenced to v ss ) (note 1.) symbol parameter value unit v dd dc supply voltage range 0.5 to +18.0 v v in , v out input or output voltage range (dc or transient) 0.5 to v dd + 0.5 v i in , i out input or output current (dc or transient) per pin 10 ma p d power dissipation, per package (note 2.) 500 mw t a ambient temperature range 55 to +125 c t stg storage temperature range 65 to +150 c t l lead temperature (8second soldering) 260 c 1. maximum ratings are those values beyond which damage to the device may occur. 2. temperature derating: plastic ap and d/dwo packages: 7.0 mw/ c from 65 c to 125 c this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open. http://onsemi.com a = assembly location wl, l = wafer lot yy, y = year ww, w = work week device package shipping ordering information mc14562bcp pdip14 25/rail marking diagrams 1 14 pdip14 p suffix case 646 mc14562bcp awlyyww
mc14562b http://onsemi.com 2 pin assignment 11 12 13 14 8 9 10 5 4 3 2 1 7 6 q16 nc data q32 v dd q80 q48 nc q128 q96 q64 v ss q112 clock nc = no connection block diagram 10 13 9 1 8 2 6 3 q128 q112 q96 q80 q64 q48 q32 q16 12 5 data clock v dd = pin 14 v ss = pin 7 pins 4 and 11 not used. logic diagram 1 2 3 16173233484964 clock5 data in12 65 80 81 96 d c q 97 d c q 112 d c q 113 d c q 128 10q16 13q32 9q48 1q64 8q80 2q96 6q112 3q128 d c qd c qd c qd c q d c qd c qd c qd c q d c qd c qd c qd c qd c qd c q
mc14562b http://onsemi.com 3 ????????????????????????????????? ????????????????????????????????? electrical characteristics (voltages referenced to v ss ) v dd 55 c 25 c 125 c characteristic symbol v dd vdc min max min typ (3.) max min max unit output voltage a0o level v in = v dd or 0 v ol 5.0 10 15 e e e 0.05 0.05 0.05 e e e 0 0 0 0.05 0.05 0.05 e e e 0.05 0.05 0.05 vdc a1o level v in = 0 or v dd v oh 5.0 10 15 4.95 9.95 14.95 e e e 4.95 9.95 14.95 5.0 10 15 e e e 4.95 9.95 14.95 e e e vdc input voltage a0o level (v o = 4.5 or 05 vdc) (v o = 9.0 or 1.0 vdc) (v o = 13.5 or 1.5 vdc) v il 5.0 10 15 e e e 1.5 3.0 4.0 e e e 2.25 4.50 6.75 1.5 3.0 4.0 e e e 1.5 3.0 4.0 vdc a1o level (v o = 0.5 or 4.5 vdc) (v o = 1.0 or 9.0 vdc) (v o = 1.5 or 13.5 vdc) v ih 5.0 10 15 3.5 7.0 11 e e e 3.5 7.0 11 2.75 5.50 8.25 e e e 3.5 7.0 11 e e e vdc output drive current (v oh = 2.5 vdc) source (v oh = 4.6 vdc) (v oh = 9.5 vdc) (v oh = 13.5 vdc) i oh 5.0 5.0 10 15 3.0 0.64 1.6 4.2 e e e e 2.4 0.51 1.3 3.4 4.2 0.88 2.25 8.8 e e e e 1.7 0.36 0.9 2.4 e e e e madc (v ol = 0.4 vdc) sink (v ol = 0.5 vdc) (v ol = 1.5 vdc) i ol 5.0 10 15 0.64 1.6 4.2 e e e 0.51 1.3 3.4 0.88 2.25 8.8 e e e 0.36 0.9 2.4 e e e madc input current i in 15 e 0.1 e 0.00001 0.1 e 1.0 m adc input capacitance (v in = 0) c in e e e e 5.0 7.5 e e pf quiescent current (per package) i dd 5.0 10 15 e e e 5.0 10 20 e e e 0.010 0.020 0.030 5.0 10 20 e e e 150 300 600 m adc total supply current (4.) (5.) (dynamic plus quiescent, per package) (c l = 50 pf on all outputs, all buffers switching) i t 5.0 10 15 i t = (1.94 m a/khz) f + i dd i t = (3.81 m a/khz) f + i dd i t = (5.52 m a/khz) f + i dd m adc 3. data labelled atypo is not to be used for design purposes but is intended as an indication of the ic's potential performance. 4. the formulas given are for the typical characteristics only at 25 c. 5. to calculate total supply current at loads other than 50 pf: i t (c l ) = i t (50 pf) + (c l 50) vfk where: i t is in m a (per package), c l in pf, v = (v dd v ss ) in volts, f in khz is input frequency, and k = 0.004.
mc14562b http://onsemi.com 4 ????????????????????????????????? ????????????????????????????????? switching characteristics (6.) (c l = 50 pf, t a = 25 c) characteristic symbol v dd min typ (7.) max unit output rise and fall time t tlh , t thl = (1.5 ns/pf) c l + 25 ns t tlh , t thl = (0.75 ns/pf) c l + 12.5 ns t tlh , t thl = (0.55 ns/pf) c l + 9.5 ns t tlh , t thl 5.0 10 15 e e e 100 50 40 200 100 80 ns propagation delay time clock to q t plh , t phl = (1.7 ns/pf) c l + 515 ns t plh , t phl = (0.66 ns/pf) c l + 217 ns t plh , t phl = (0.5 ns/pf) c l + 145 ns t plh , t phl 5.0 10 15 e e e 600 250 170 1200 500 340 ns clock pulse width (50% duty cycle) t wh 5.0 10 15 600 220 150 300 110 75 e e e ns clock pulse frequency f cl 5.0 10 15 e e e 1.9 5.6 8.0 1.1 3.0 4.0 mhz data to clock setup time t su(1) 5.0 10 15 20 10 0 170 64 60 e e e ns t su(0) 5.0 10 15 20 10 0 91 58 48 e e e ns data to clock hold time t h(1) 5.0 10 15 350 165 155 263 109 100 e e e ns t h(0) 5.0 10 15 350 200 140 267 140 93 e e e ns clock input rise and fall times t r , t f 5.0 10 15 e e e e e e 15 5 4 m s 6. the formulas given are for the typical characteristics only at 25 c. 7. data labelled atypo is not to be used for design purposes but is intended as an indication of the ic's potential performance .
mc14562b http://onsemi.com 5 figure 1. power dissipation test circuit and waveforms v dd data clock q128 q112 q96 q80 q64 q48 q32 q16 v ss 7 i d 500 m f c l c l c l c l c l c l c l c l f o clock data (f = 1/2 f o ) v dd v ss v dd v ss
mc14562b http://onsemi.com 6 timing diagram pulse 1 pin no.'s clock5 data in12 q1610 q3213 q283 pulse 16 pulse 32 pulse 128 ac test waveforms note: the remaining databit outputs (q32, q48, q64, q80, q96, q112 and q128) will occur at clock pulse 32, 48, 64, 80, 96, 112, 128 in the same relationship as q16. v dd v ss v dd v ss v dd v ss v dd v ss v dd v ss v dd v ss clock data in q16 clock data in q16 pulse 1 pulse 2 pulse 16 pulse 17 50% 50% 50% 90% 10% 50% t wh t wl t r t f 50% 50% t su(0) t h(0) 50% 90% 10% t phl t thl pulse 1 pulse 2 pulse 16 pulse 17 50% 50% 50% t wh t wl 50% 50% 50% t su(1) t h(1) 50% 90% 10% t thl t plh
mc14562b http://onsemi.com 7 package dimensions p suffix plastic dip package case 64606 issue m 17 14 8 b a dim min max min max millimeters inches a 0.715 0.770 18.16 18.80 b 0.240 0.260 6.10 6.60 c 0.145 0.185 3.69 4.69 d 0.015 0.021 0.38 0.53 f 0.040 0.070 1.02 1.78 g 0.100 bsc 2.54 bsc h 0.052 0.095 1.32 2.41 j 0.008 0.015 0.20 0.38 k 0.115 0.135 2.92 3.43 l m --- 10 --- 10 n 0.015 0.039 0.38 1.01 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. f hg d k c seating plane n t 14 pl m 0.13 (0.005) l m j 0.290 0.310 7.37 7.87
mc14562b http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402745 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc14562b/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk
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